Publications

A 3.25GHz Large-Integer Extended GCD Accelerator in 12nm

Kavya Sreedhar, Gedeon Nyengele, Mark Horowitz, Christopher Torng

European Solid-State Electronics Research Conference (ESSERC), September 2024

– DOI – PDF – Slides –

Onyx: A Programmable Accelerator for Sparse Tensor Algebra

Kalhan Koul, Maxwell Strange, Jackson Melchert, Alex Carsello, Yuchen Mei, Olivia Hsu, Taeyoung Kong, Po-Han Chen, Huifeng Ke, Keyi Zhang, Qiaoyi Liu, Gedeon Nyengele, Akhilesh Balasingam, Jayashree Adivarahan, Ritvik Sharma, Zhouhua Xie, Christopher Torng, Joel S Emer, Fredrik Kjolstad, Mark Horowitz, Priyanka Raina

Symposium on High Performance Chips (Hot Chips), August 2024

– DOI –

AHA: An Open-Source Framework for Co-design of Programmable Accelerators and Compilers

Kalhan Koul, Jackson Melchert, Keyi Zhang, Taeyoung Kong, Maxwell Strange, Olivia Hsu, Qiaoyi Liu, Jeff Setter, Ross Daly, Caleb Donovick, Alex Carsello, Leonard Truong, Po-Han Chen, Yuchen Mei, Zhouhua Xie, Kathleen Feng, Gedeon Nyengele, Dillon Huff, Kavya Sreedhar, Huifeng Ke, Ankita Nayak, Rajsekhar Setaluri, Stephen Richardson, Christopher Torng, Pat Hanrahan, Clark Barrett, Mark Horowitz, Fredrik Kjolstad, Priyanka Raina

Workshop on Open-Source Computer Architecture Research (OSCAR) co-located with ISCA, June 2024

Onyx: A 12nm 756 GOPS/W Coarse-Grained Reconfigurable Array for Accelerating Dense and Sparse Applications

Kalhan Koul, Maxwell Strange, Jackson Melchert, Alex Carsello, Yuchen Mei, Olivia Hsu, Taeyoung Kong, Po-Han Chen, Huifeng Ke, Keyi Zhang, Qiaoyi Liu, Gedeon Nyengele, Akhilesh Balasingam, Jayashree Adivarahan, Ritvik Sharma, Zhouhua Xie, Christopher Torng, Joel Emer, Fredrik Kjolstad, Mark Horowitz, Priyanka Raina

IEEE Symposium on VLSI Technology and Circuits (VLSI), June 2024

– DOI –

Amber: A 16-nm System-on-Chip With a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra

Kathleen Feng, Taeyoung Kong, Kalhan Koul, Jackson Melchert, Alex Carsello, Qiaoyi Liu, Gedeon Nyengele, Maxwell Strange, Keyi Zhang, Ankita Nayak, Jeff Setter, James Thomas, Kavya Sreedhar, Po-Han Chen, Nikhil Bhagdikar, Zach A Myers, Brandon D’Agostino, Pranil Joshi, Stephen Richardson, Christopher Torng, Mark Horowitz, Priyanka Raina

IEEE Journal of Solid-State Circuits (JSSC), March 2024

– DOI –

Building First-Order Energy Modeling Intuition in Computer Architecture Lectures

Christopher Torng

Workshop on Computer Architecture Education (WCAE) co-located with ISCA, June 2023

– PDF – DOI –

A Fast Open-Source Extended GCD Accelerator

Kavya Sreedhar, Mark Horowitz, Christopher Torng

Workshop on Open-Source Computer Architecture Research (OSCAR) co-located with ISCA, June 2023

Ankita Nayak, Keyi Zhang, Raj Setaluri, Alex Carsello, Makai Mann, Christopher Torng, Stephen Richardson, Rick Bahr, Pat Hanrahan, Mark Horowitz, and Priyanka Raina

ACM Transactions on Reconfigurable Technology and Systems (TRETS), April 2023

– DOI –

Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays

Jackson Melchert*, Keyi Zhang*, Yuchen Mei, Mark Horowitz, Christopher Torng, Priyanka Raina

(* = denotes equal contribution)

IEEE Computer Architecture Letters (CAL), April 2023

– DOI –

AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers

Kalhan Koul, Jackson Melchert, Kavya Sreedhar, Leonard Truong, Gedeon Nyengele, Keyi Zhang, Qiaoyi Liu, Jeff Setter, Po-Han Chen, Yuchen Mei, Maxwell Strange, Ross Daly, Caleb Donovick, Alex Carsello, Taeyoung Kong, Kathleen Feng, Dillon Huff, Ankita Nayak, Rajsekhar Setaluri, James Thomas, Nikhil Bhagdikar, David Durst, Zachary Myers, Nestan Tsiskaridze, Stephen Richardson, Rick Bahr, Kayvon Fatahalian, Pat Hanrahan, Clark Barrett, Mark Horowitz, Christopher Torng, Fredrik Kjolstad, Priyanka Raina

ACM Transactions on Embedded Computing Systems (TECS), January 2023

– DOI –

Hardware Abstractions and Hardware Mechanisms to Support Multi-Task Execution on Coarse-Grained Reconfigurable Arrays

Taeyoung Kong, Kalhan Koul, Priyanka Raina, Mark Horowitz, Christopher Torng

Workshop on Democratizing Domain-Specific Accelerators (WDDSA) co-located with MICRO, October 2022

– PDF –

A Fast Large-Integer Extended GCD Algorithm and Hardware Design for Verifiable Delay Functions and Modular Inversion

Kavya Sreedhar, Mark Horowitz, and Christopher Torng

Conference on Cryptographic Hardware and Embedded Systems (CHES), September 2022

– PDF – Slides – Video – DOI – Artifact –

mflowgen: A Modular Flow Generator and Ecosystem for Community-Driven Physical Design

Alex Carsello, James Thomas, Ankita Nayak, Po-Han Chen, Mark Horowitz, Priyanka Raina, and Christopher Torng

ACM/IEEE Design Automation Conference (DAC), July 2022

– PDF – DOI –

Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration

Kathleen Feng, Alex Carsello, Taeyoung Kong, Kalhan Koul, Qiaoyi Liu, Jackson Melchert, Gedeon Nyengele, Maxwell Strange, Keyi Zhang, Ankita Nayak, Jeff Setter, James Thomas, Kavya Sreedhar, Po-Han Chen, Nikhil Bhagdikar, Zachary Myers, Brandon D’Agostino, Pranil Joshi, Stephen Richardson, Rick Bahr, Christopher Torng, Mark Horowitz, Priyanka Raina

Symposium on High Performance Chips (Hot Chips), August 2022

Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra

Alex Carsello, Kathleen Feng, Taeyoung Kong, Kalhan Koul, Qiaoyi Liu, Jackson Melchert, Gedeon Nyengele, Maxwell Strange, Keyi Zhang, Ankita Nayak, Jeff Setter, James Thomas, Kavya Sreedhar, Po-Han Chen, Nikhil Bhagdikar, Zachary Myers, Brandon D’Agostino, Pranil Joshi, Stephen Richardson, Rick Bahr, Christopher Torng, Mark Horowitz, and Priyanka Raina

IEEE Symposium on VLSI Technology and Circuits (VLSI), June 2022

– DOI – Best Demo Paper Award –

Enabling Reusable Physical Design Flows with Modular Flow Generators

Alex Carsello, James Thomas, Ankita Nayak, Po-Han Chen, Mark Horowitz, Priyanka Raina, and Christopher Torng

Preprint, November 2021

– PDF – arXiv –

Ultra-Elastic CGRAs for Irregular Loop Specialization

Christopher Torng, Peitian Pan, Yanghui Ou, Cheng Tan, Christopher Batten

International Symposium on High-Performance Computer Architecture (HPCA), February 2021

– PDF – Slides – Video – DOI – Artifact –

Creating An Agile Hardware Design Flow

Rick Bahr, Clark Barrett, Nikhil Bhagdikar, Alex Carsello, Ross Daly, Caleb Donovick, David Durst, Kayvon Fatahalian, Kathleen Feng, Pat Hanrahan, Teguh Hofstee, Mark Horowitz, Dillon Huff, Fredrik Kjolstad, Taeyoung Kong, Qiaoyi Liu, Makai Mann, Jackson Melchert, Ankita Nayak, Aina Niemetz, Gedeon Nyengele, Priyanka Raina, Stephen Richardson, Raj Setaluri, Jeff Setter, Kavya Sreedhar, Maxwell Strange, James Thomas, Christopher Torng, Leonard Truong, Nestan Tsiskaridze, and Keyi Zhang

ACM/IEEE Design Automation Conference (DAC), July 2020

– PDF – Slides – Video – DOI –

Software, Architecture, and VLSI Co-Design for Fine-Grain Voltage and Frequency Scaling

Christopher Torng

PhD Thesis, December 2019

– PDF – Slides –

Evaluating Celerity: A 16nm 695 Giga-RISC-V Instructions/s Manycore Processor with Synthesizable PLL

Austin Rovinski, Chun Zhao, Khalid Al-Hawaj, Paul Gao, Shaolin Xie, Christopher Torng, Scott Davidson, Aporva Amarnath, Luis Vega, Bandhav Veluri, Anuj Rao, Tutu Ajayi, Julian Puscar, Steve Dai, Ritchie Zhao, Dustin Richmond, Zhiru Zhang, Ian Galton, Christopher Batten, Michael B. Taylor, and Ronald G. Dreslinski

IEEE Solid-State Circuits Letters, December 2019

– PDF – DOI –

PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks

Cheng Tan, Yanghui Ou, Shunning Jiang, Peitian Pan, Christopher Torng, Shady Agwa, and Christopher Batten

IEEE International Conference on Computer Design (ICCD), November 2019

– PDF – Slides – DOI –

A 1.4 GHz 695 Giga RISC-V Inst/s 496-core Manycore Processor with Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS

Austin Rovinski, Chun Zhao, Khalid Al-Hawaj, Paul Gao, Shaolin Xie, Christopher Torng, Scott Davidson, Aporva Amarnath, Luis Vega, Bandhav Veluri, Anuj Rao, Tutu Ajayi, Julian Puscar, Steve Dai, Ritchie Zhao, Dustin Richmond, Zhiru Zhang, Ian Galton, Christopher Batten, Michael B. Taylor, and Ron G. Dreslinski

IEEE Symposium on VLSI Circuits (VLSI), June 2019

– PDF – DOI –

An Open-Source Python-Based Hardware Generation, Simulation, and Verification Framework

Shunning Jiang, Christopher Torng, and Christopher Batten

Workshop on Open-Source EDA Technology (WOSET) co-located with ICCAD, November 2018

– PDF – Slides – Poster –

A New Era of Silicon Prototyping in Computer Architecture Research

Christopher Torng, Shunning Jiang, Khalid Al-Hawaj, Ivan Bukreyev, Berkin Ilbeyi, Tuan Ta, Lin Cheng, Julian Puscar, Ian Galton, and Christopher Batten

RISC-V Day Workshop co-located with MICRO, October 2018

– PDF – Slides –

A Modular Digital VLSI Flow for High-Productivity SoC Design

Brucek Khailany, Evgeni Krimer, Rangharajan Venkatesan, Jason Clemons, Joel Emer, Matthew Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Pinckney, Yakun Sophia Shao, Shreesha Srinath, Christopher Torng, Sam (Likun) Xi, Yanqing Zhang, Brian Zimmer

ACM/IEEE Design Automation Conference (DAC), June 2018

– PDF – DOI – Code –

The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips

Scott Davidson, Shaolin Xie, Christopher Torng, Khalid Al-Hawaj, Austin Rovinski, Tutu Ajayi, Luis Vega, Chun Zhao, Ritchie Zhao, Steve Dai, Aporva Amarnath, Bandhav Veluri, Paul Gao, Anuj Rao, Gai Liu, Rajesh K. Gupta, Zhiru Zhang, Ronald G. Dreslinski, Christopher Batten, and Michael B. Taylor

IEEE Micro – Special issue for top picks from Hot Chips 29, March/April 2018

– PDF – DOI –

Four Monolithically Integrated Switched-Capacitor DC-DC Converters with Dynamic Capacitance Sharing in 65-nm CMOS

Ivan Bukreyev, Christopher Torng, Waclaw Godycki, Christopher Batten, and Alyssa Apsel

IEEE Transactions on Circuits and Systems I (TCAS I), November 2017

– PDF – DOI –

Using Intra-Core Loop-Task Accelerators to Improve the Productivity and Performance of Task-Based Parallel Programs

Ji Kim, Shunning Jiang, Christopher Torng, Moyang Wang, Shreesha Srinath, Berkin Ilbeyi, Khalid Al-Hawaj, Christopher Batten

IEEE/ACM International Symposium on Microarchitecture (MICRO), October 2017

– PDF – Slides – Poster – DOI –

Experiences Using the RISC-V Ecosystem to Design an Accelerator-Centric SoC in TSMC 16nm

Tutu Ajayi, Khalid Al-Hawaj, Aporva Amarnath, Steve Dai, Scott Davidson, Paul Gao, Gai Liu, Anuj Rao, Austin Rovinski, Ningxiao Sun, Christopher Torng, Luis Vega, Bandhav Veluri, Shaolin Xie, Chun Zhao, Ritchie Zhao, Christopher Batten, Ronald G. Dreslinski, Rajesh K. Gupta, Michael B. Taylor, Zhiru Zhang

Workshop on Computer Architecture Research with RISC-V (CARRV) co-located with MICRO, October 2017

– PDF – Slides – Open-Source Code – Site –

Celerity: An Open Source RISC-V Tiered Accelerator Fabric

Tutu Ajayi, Khalid Al-Hawaj, Aporva Amarnath, Steve Dai, Scott Davidson, Paul Gao, Gai Liu, Atieh Lotfi, Julian Puscar, Anuj Rao, Austin Rovinski, Loai Salem, Ningxiao Sun, Christopher Torng, Luis Vega, Bandhav Veluri, Xiaoyang Wang, Shaolin Xie, Chun Zhao, Ritchie Zhao, Christopher Batten, Ronald G. Dreslinski, Ian Galton, Rajesh K. Gupta, Patrick P. Mercier, Mani Srivastava, Michael B. Taylor, Zhiru Zhang

Symposium on High Performance Chips (Hot Chips), August 2017

– Slides – Open-Source Code –

Experiences Using A Novel Python-Based Hardware Modeling Framework For Computer Architecture Test Chips

Christopher Torng, Moyang Wang, Bharath Sudheendra, Nagaraj Murali, Suren Jayasuriya, Shreesha Srinath, Taylor Pritchard, Robin Ying, and Christopher Batten

Poster and Abstract at Symposium on High Performance Chips (Hot Chips), August 2016

– PDF – Slides – Poster – DOI –

Asymmetry-Aware Work-Stealing Runtimes

Christopher Torng, Moyang Wang, and Christopher Batten

ACM/IEEE International Symposium on Computer Architecture (ISCA), June 2016

– PDF – Slides – Addendum – DOI –

Enabling Realistic Fine-Grain Voltage Scaling with Reconfigurable Power Distribution Networks

Waclaw Godycki*, Christopher Torng*, Ivan Bukreyev, Alyssa Apsel, and Christopher Batten

(* = denotes equal contribution)

IEEE/ACM International Symposium on Microarchitecture (MICRO), December 2014

– PDF – Slides – DOI –

Microarchitectural Mechanisms to Exploit Value Structure in SIMT Architectures

Ji Kim, Christopher Torng, Shreesha Srinath, Derek Lockhart, and Christopher Batten

ACM/IEEE International Symposium on Computer Architecture (ISCA), June 2013

– PDF – DOI –