EE 599: Special Topic on Complex Digital ASIC System Design
- Instructor: Professor Christopher Torng
- Term: Fall 2023
- Units: 4
This is a new project-based course in which you will leverage all of your architecture and VLSI experience to build hardware for an interesting application of your choice and then tape out your own chip within fifteen weeks in an advanced Intel 16 technology!
Logistics: You will be asked to form small groups of 4-5 students. After the design is fabricated, you will get your chip back in a few months. All teams must include at least two students who commit to remain available for your post-silicon chip bringup in an ASIC prototyping lab when your chips are back from the fab. This completes the full chip design cycle, making this course useful for anyone who is thinking about designing a chip in their research or in their careers after graduation.
Shuttle space for this course offering is donated generously by Intel Corporation 
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Frequently Asked Questions
– Who is this course aimed at, PhD / MS / undergraduate? — PhD students get first pick at seats and are intended to use this experience to drive their research. MS students and advanced, highly motivated undergrads are also able to enroll if there are seats remaining.
– What do I need to do in preparation? — You will be forming a small team and coming up with a project proposal for an application that is interesting to you that you wish to build a chip for. PhD students can pick something relevant to their research (e.g., a simple application-specific hardware accelerator for an application you are studying). The proposals will be discussed with the course staff to help you gauge how feasible or ambitious the project is. You should have a high chance to produce a working chip with staff support.
– What if I am a non-digital student (mixed signal / analog)? — There is another USC course aimed at analog tapeout (EE 505). However, if students wish to take EE 599 and are interested in building small mixed-signal and analog chips, please discuss with course staff. Note that the lectures will be driven from a more digital perspective.
– If we are building real silicon, what about grades? — This is a graduate course, and it culminates in a letter grade. However, given that you are putting so much effort into producing silicon, we are much more invested in your chip actually working! A working chip feeds into your research (if you are a PhD student) or can greatly enhance your resume (if you are a MS or undergraduate student). Being successful will require significant attention to detail and much effort. The grading approach will therefore align with project-oriented courses, and the majority of the grade aligns with the milestones for producing successful, working silicon (e.g., design reviews, proposals, weekly syncups). There is no significant written exam component to this course.
EE 557: Computer Systems Architecture
- Instructor: Professor Christopher Torng
- Term: Spring 2023
- Units: 4
This course aims to familiarize students with the modern era of computer architecture, including the single-core era, the multi-core era, and finally the accelerator era. The course objective is to establish a strong understanding of both the design concepts (e.g., specific out-of-order execution techniques, specific data-parallel accelerators) and the design-space exploration concepts that help reason about the murky space surrounding each classic design point (e.g., by using first-order performance and energy estimation models, roofline models, etc.).
The first main part of the course focuses on classic advanced processor design concepts. Topics include superscalar execution, out-of-order execution, register renaming, memory disambiguation, branch prediction, and speculative execution. The second main part of this course focuses on parallel computer architecture and aims to cover the aspects of memories and interconnection networks that influence homogeneous and heterogeneous multicore processors. The final part of this course aims to lift from traditional computer architecture into the accelerator design space, which features interactions between software and hardware and the perspectives of co-designing across abstractions.
At the end of this course, students will be ready to work in industry or on research in the area of computer architecture. They will have the knowledge to design complex systems and to balance computer systems for a given application. Moreover, they will have gained practical experience in using architectural-level design tools including architecture simulators, area/complexity estimators, and power/energy estimators, enabling them to design and evaluate large-scale systems.